Integrated circuits like memory circuits comprise memory cells in which digital information are stored. DRAMs (Dynamic Random Access Memories) comprise memory cells in which the information is stored by electrical charges accumulated in a capacitor. A capacitor of a memory cell is usually formed as a stacked capacitor or as a deep trench capacitor. A deep trench capacitor is formed by etching a deep trench into a substrate, forming a first electrode in a substrate region surrounding the sidewalls and the bottom of the deep trench, by depositing a capacitor dielectric on the bottom and on the sidewalls of the trench and by filling the trench with a conductive material thereby forming the second electrode. The second electrode is connected to a source/drain-region of a transistor. Another source/drain-region of the transistor is connected to the bitline. The gate electrode of the transistor is connected to the wordline.
Due to the shrinking dimensions of memory cells of future generations of memory products, it becomes increasingly difficult to store a sufficiently large amount of electrical charges in the memory cell. If a storage capacitor is formed as a deep trench capacitor, reducing memory cell dimensions requires decreasing the lateral cross-section of the deep trench capacitor. The maximum depth of a deep trench capacitor cannot be increased without narrowing the process window of the process technology. Accordingly, the capacitance of an integrated capacitor decreases with shrinking memory cell dimensions unless appropriate measures are taken to enlarge the capacitance per capacitor plate surface of the integrated capacitor. A sufficiently high total capacitance of an integrated capacitor is required for preserving a sufficiently large amount of charges during the refresh time in order to allow safe reading of the stored digital information.
It is known that a sacrificial undoped layer of hemispherical grain silicon (HSG) can be provided as a mask over polysilicon. The polysilicon layer is etched using the HSG-silicon layer as an etching mask. The HSG-silicon layer is then removed from the polysilicon layer. It is also known to form mesopores in a substrate by annealing the substrate in a furnace in an atmosphere containing oxygen.
Another approach used for deep trench capacitors is widening a lower trench portion. The surface of the capacitor plates is increased. Trench-widening is called “bottling” and is performed by wet etching of a lower trench portion below an upper trench portion where an isolation collar is to be formed later. During wet etching, an upper trench portion is protected by a protecting layer in order to preserve lateral trench dimensions in the upper trench portion close to the substrate surface.
Widening the cross-section of a lower trench portion, however, increases the risk of short-circuits between deep trench capacitors of adjacent memory cells. Furthermore, this technique is only applicable to deep trench capacitors but not to stacked capacitors.
Though the hemispherical grain technique increases the capacitance of deep trench capacitors and stacked capacitors to some extent, techniques for further increasing the capacitance are required.